The present invention pertains to a technique to improve emitter tip uniformity on large area passive matrix cold cathode field emission displays and, in particular, to the resulting improved product.
Field emission display (FED) technology utilizes a matrix addressable array of pointed, thin film, cold field emission cathodes in combination with a phosphor luminescent screen. U.S. Pat. No. 4,940,916 discloses an electron source, with micropoint emissive cathodes, and display means by cathodoluminescence excited by field emission from the electron source. Each cathode has an electrically conductive layer, a continuous resistive layer on the conductive layer and a patterned array of a plurality of micropoints. The display includes a cathodoluminescent anode facing the source. A further example can be found in U.S. Pat. No. 5,210,472, the disclosures of both of these patents being incorporated herein by reference. An emissive flat panel display operates on the principles of cathodoluminescent phosphors excited by cold cathode field emission electrons. A faceplate having a cathodoluminescent phosphor coating receives patterned electron bombardment from an opposing baseplate thereby providing a light image which can be seen by a viewer. The faceplate is separated from the base plate by a vacuum gap and, in some embodiments, the two plates are prevented from collapsing together by physical standoffs or spacers fixed between them.
The baseplate of a field emission display is comprised of arrays of emission sites (emitters) which are typically sharp cones that produce electron emission in the presence of an intense electric field, an extraction grid disposed relative to the sharp emitters provides the intense positive voltage for the electric field and a means for addressing and activating the generation of electron beams from those sites. Varying the charge which is delivered to the phosphor in a given pixel from an emission array will vary the light output (brightness) of the pixel associated with it. Two techniques for varying the charge delivered by an emission array are to either vary the time period of activation (duty cycle) or to vary the emission current.
Fabrication of FEDs utilizes high resolution lithography and etching to create openings in a metal-semiconductor-dielectric sandwich. Problems can arise in either, or both, over-etching and under-etching the semiconductor layer used to form the emitter tips. Previous processing sequences presented difficulties in adequately etching the tip layer without over etching the underlying resistive layer. The result was shorted emitter tips (under-etching) or variable resistive layer thicknesses for different areas of the array (over-etching). Any variation of the thickness of the resistor layer results in low pixel yield and poor uniformity across the array. By following the sequence specified by the present invention, the uniformity and yield problems of the prior art are minimized. For example, in addition to the above mentioned patents, see U.S. Pat. Nos. 3,500,102; 5,212,426; and 5,359,256, all of which are incorporated herein by reference.